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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
FEATURES
* * * * * * * * * * * * * * * * Form, Fit, and Function Compatible with the Intel(R) 8X44 Packaging options available: 40 Pin Plastic Dual In-Line Package (PDIP), 44 Pin Plastic Leaded Chip Carrier (PLCC) 8-Bit Control Unit 8-Bit Arithmetic-Logic Unit with 16-Bit multiplication and division 12 MHz clock Four 8-Bit Input / Output ports Two 16-Bit Timer/Counters Serial Interface Unit with SDLC/HDLC compatibility 2.4 Mbps maximum serial data rate Two Level Priority Interrupt System 5 Interrupt Sources Internal Clock prescaler and Phase generator 192 Bytes of Read/Write Data Memory Space 64kB External Program Memory Space 64kB External Data Memory Space 4kB Internal ROM (IA8044 only)
IA8044/IA8344 Variants
IA8044 IA8344 4kB internal ROM with R0117 version 2.1 firmware, 192 byte internal RAM (Expandable to 256 Bytes), 64kB external program and data space. 192 byte internal RAM, 64kB external program and data space.
The IA8044/IA8344 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA8044/IA8344 including functional and I/O descriptions, electrical characteristics, and applicable timing.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Package Pinout
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 (RTS) P1.6 (CTS) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4
(SCLK/T1) P3.5
P1.4
P1.3
P0.1
P0.2 (41)
VCC
P1.0
(2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20)
40 Pin DIP
(39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21)
P0.0 (AD0) P0.1 (AD1)
(44)
(43)
(42)
P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10)
P1.5 P1.6 P1.7 RST/VPD P3.0 N.C. P3.1 P3.2 P3.3 P3.4 P3.5
(7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28)
(40)
(6)
(5)
(4)
(3)
(2)
(1)
P0.2 (AD2)
P0.0
N.C.
P0.3
P1.2
P1.1
(1)
IA8X44
(40)
VCC
(39) (38)
P0.4 P0.5 P0.6 P0.7 EA N.C. ALE PSEN P2.7 P2.6 P2.5
IA8X44 44 Pin LCC
(37) (36) (35) (34) (33) (32) (31) (30) (29)
(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 VSS
VSS
P2.0
P2.3
XTAL2
XTAL1
P3.6
P3.7
P2.1
P2.1 (A9) P2.0 (A8)
DESCRIPTION
The IA8044/IA8344 is a form, fit and function compatible part to the Intel(R) 8X44 SDLC communications controller. The IA8044/IA8344 is a Fast Single-Chip 8-Bit Microcontroller with an integrated SDLC/HDLC serial interface controller. The IA8044/IA8344 is a fully functional 8Bit Embedded Controller that executes all ASM51 instructions and has the same instruction set as the Intel 80C51. The IA8044/IA8344 can access the instructions from two types of program memory, serves software and hardware interrupts, provides an interface for serial communications and a timer system. The IA8044/IA8344 is fully compatible with the Intel(R) 8X44 series. The functional block diagram is shown below.
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P2.2
P2.4
N.C.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Functional Block Diagram
Preliminary Data Sheet
As of Production Version 00
I/O for Memory, SIU, DMA, Interrupts, Timers
Port 0 ADDR/DATA/IO
Port 2 ADDR/DATA/IO
Port 1 SPCL FUNC/IO
Port 3 SPCL FUNC/IO
Memory Control XTAL Reset Clock Gen. & Timing 192x8Dual Port RAM C8051 CPU Control
Address/Data
Interrupts
SIU
Timers
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
I/O Characteristics
The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. The table below provides the I/O description of the IA8044 and the IA8344. Name RST ALE PSEN EA P0.7 - P0.0 P1.7 - P1.0 P2.7 - P2.0 P3.7 - P3.0 Type I O O I I/O I/O I/O I/O Description Reset. This pin when held high for two machine cycles while the oscillator is running will cause the chip to reset. Address Latch Enable. Used to latch the address on the falling edge for external memory accesses. Program Store Enable. When low acts as an output enable for external program memory. External Access. When held low EA will cause the IA8044/IA8344 to fetch instructions from external memory. Port 0. 8 bit I/O port and low order multiplexed address/data byte for external accesses. Port 1. 8 bit I/O port. Two bits have alternate functions, P1.6 (RTS) and P1.7 (CTS). Port 2. 8 bit I/O port. It also functions as the high order address byte during external accesses. Port 3. 8 bit I/O port. Port 3 bits also have alternate functions as described below. P3.0 - RXD. Receive data input for SIU or direction control for P3.1 dependent upon datalink configuration. P3.1 - TXD. Transmit data output for SIU or data input/output dependent upon datalink configuration. Also enables diagnostic mode when cleared. P3.2 - INT0. Interrupt 0 input or gate control input for counter 0. P3.3 - INT1. Interrupt 1 input or gate control input for counter 1. P3.4 - T0. Input to counter 0. P3.5 - SCLK/T1. SCLK input to SIU or input to counter 1. P3.6 - WR. External memory write signal. P3.7 - RD. External memory read signal. Crystal Input 1. Connect to VSS when external clock is used on XTAL2. May be connected to a crystal (with XTAL2), or may be driven directly with a clock source (XTAL2 not connected). Crystal Input 2. May be connected to a crystal (with XTAL1), or may be driven directly with an inverted clock source (XTAL1 tied to ground). Ground. +5V power.
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XTAL1
I
XTAL2 VSS VCC
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Memory Organization Program Memory
Preliminary Data Sheet
As of Production Version 00
Program Memory includes interrupt and Reset vectors. The interrupt vectors are spaced at 8byte intervals, starting from 0003H for External Interrupt 0.
Reset Vectors
Location 0003H 000BH 0013H 001BH 0023H Service External Interrupt 0 Timer 0 overflow External Interrupt 1 Timer 1 overflow SIU Interrupt
These locations may be used for program code, if the corresponding interrupts are not used (disabled). The Program Memory space is 64K, from 0000H to FFFFH. The lowest 4K of program code (0000H to 0FFFH) can be fetched from external or internal Program Memory. This selection is made by strapping pin `EA' (External Address) to GND or VCC. If during reset, `EA' is held low, all the program code is fetched from external memory. If, during reset, `EA' is held high, the lowest 4K of program code (0000H to 0FFFH) is fetched from internal memory (ROM).
Data Memory External Data Memory
The IA8044/IA8344 Microcontroller core incorporates the Harvard architecture, with separate code and data spaces. The code from external memory is fetched by `psen' strobe, while data is read from RAM by bit 7 of P3 (read strobe) and written to RAM by bit 6 of P3 (write strobe). The External Data Memory space is active only by addressing through use of the 16 bit Data Pointer Register (DPTR). A smaller subset of external data memory (8 bit addressing) may be accessed by using the MOVX instruction with register indexed addressing.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Internal Data Memory
Preliminary Data Sheet
As of Production Version 00
The Internal Data Memory address is always 1 byte wide. The memory space is 192 bytes large (00H to BFH), and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Internal memory which overlaps the SFR address space is only accessible by indirect addressing.
Internal Memory
FFh
BFh Special Function Registers Addressable BITS in SFRs (128 BITS)
Indirect Addressing
RAM
80h 7Fh
80h
Direct Addressing
30h 2Fh Bit Addressable Memory 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h Internal Data Ram 8044 Internal Data Memory Addresses 00h to FFh Register Bank 3 Register Bank 2 Register Bank 1 Register Bank 0
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Bit Addressable Memory Both the internal RAM and the Special Function Registers have locations that are bit addressable in addition to the byte addressable locations.
SFR Bit Addressable Locations
Byte Address
F0h E0h D8h D0h C8h B8h B0h A8h A0h 90h 88h 80h
bit 7
F7h E7h DFh D7h CFh BFh B7h AFh A7h 97h 8Fh 87h
bit 6
F6h E6h DEh D6h CEh BEh B6h AEh A6h 96h 8Eh 86h
bit 5
F5h E5h DDh D5h CDh BDh B5h ADh A5h 95h 8Dh 85h
bit 4
F4h E4h DCh D4h CCh BCh B4h ACh A4h 94h 8Ch 84h
bit 3
F3h E3h DBh D3h CBh BBh B3h ABh A3h 93h 8Bh 83h
bit 2
F2h E2h DAh D2h CAh BAh B2h AAh A2h 92h 8Ah 82h
bit 1
F1h E1h D9h D1h C9h B9h B1h A9h A1h 91h 89h 81h
bit 0
F0h E0h D8h D0h C8h B8h B0h A8h A0h 90h 88h 80h
Register
B ACC NSNR PSW STS IP P3 IE P2 P1 TCON P0
Internal RAM Bit Addressable Locations
Byte Address 30h-BFh 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 18h-1Fh 10h-17h 08h-0Fh 00h-07h bit 7 7Fh 77h 6Fh 67h 5Fh 57h 4Fh 47h 3Fh 37h 2Fh 27h 1Fh 17h 0Fh 07h bit 6 7Eh 76h 6Eh 66h 5Eh 56h 4Eh 46h 3Eh 36h 2Eh 26h 1Eh 16h 0Eh 06h bit 5 bit 4 bit 3 bit 2 Upper Internal Ram locations 7Dh 7Ch 7Bh 7Ah 75h 74h 73h 72h 6Dh 6Ch 6Bh 6Ah 65h 64h 63h 62h 5Dh 5Ch 5Bh 5Ah 55h 54h 53h 52h 4Dh 4Ch 4Bh 4Ah 45h 44h 43h 42h 3Dh 3Ch 3Bh 3Ah 35h 34h 33h 32h 2Dh 2Ch 2Bh 2Ah 25h 24h 23h 22h 1Dh 1Ch 1Bh 1Ah 15h 14h 13h 12h 0Dh 0Ch 0Bh 0Ah 05h 04h 03h 02h Register Bank 3 Register Bank 2 Register Bank 1 Register Bank 0 bit 1 79h 71h 69h 61h 59h 51h 49h 41h 39h 31h 29h 21h 19h 11h 09h 01h bit 0 78h 70h 68h 60h 58h 50h 48h 40h 38h 30h 28h 20h 18h 10h 08h 00h
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Instruction Set
Preliminary Data Sheet
As of Production Version 00
The 8X44 architecture and instruction set are identical to the 8051's. The following tables give a survey of the instruction set of the IA8044/IA8344 Microcontroller core.
Arithmetic Operations
Mnemonic ADD A,Rn ADD A, direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,direct SUBB A,@Ri SUBB A,#data INC A INC Rn INC direct INC @ Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL A,B DIV A,B DA A Description Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust accumulator Byte 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1
Cycle
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Logic Operations
Mnemonic
Preliminary Data Sheet
As of Production Version 00
Description AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator
Byte 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
Cycle 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
ANL A,Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Data Transfer
Mnemonic
Description
Preliminary Data Sheet
As of Production Version 00
Byte Cycle 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
MOV A,Rn Move register to accumulator MOV A,direct Move direct byte to accumulator MOV A,@Ri Move indirect RAM to accumulator MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register MOV Rn,direct Move direct byte to register MOV Rn,#data Move immediate data to register MOV direct,A Move accumulator to direct byte MOV direct,Rn Move register to direct byte MOV direct,direct Move direct byte to direct byte MOV direct,@Ri Move indirect RAM to direct byte MOV direct,#data Move immediate data to direct byte MOV @Ri,A Move accumulator to indirect RAM MOV @Ri,direct Move direct byte to indirect RAM MOV @ Ri, #data Move immediate data to indirect RAM MOV DPTR, #data16 Load data pointer with a 16-bit constant MOVC A,@A + DPTR Move code byte relative to DPTR to accumulator MOVC A,@A + PC Move code byte relative to PC to accumulator MOVX A,@Ri Move external RAM (8-bit addr.) to A MOVX A,@DPTR Move external RAM (16-bit addr.) to A MOVX @Ri,A Move A to external RAM (8-bit addr.) MOVX @DPTR,A Move A to external RAM (16-bit addr.) PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A,Rn Exchange register with accumulator XCH A,direct Exchange direct byte with accumulator XCH A,@Ri Exchange indirect RAM with accumulator XCHD X,@ Ri Exchange low-order nibble indir. RAM with A
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Boolean Manipulation
Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,bit ORL C,bit ORL C,bit MOV C,bit MOV bit,C Description Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit
Preliminary Data Sheet
As of Production Version 00
Byte 1 2 1 2 1 2 2 2 2 2 2 2
Cycle 1 1 1 1 1 1 2 2 2 2 1 2
Program Branches
Mnemonic ACALL addr11 LCALL addr16 RET Return RETI Return AJMP addr11 LJMP addr16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel CJNE A,direct,rel CJNE A,#data,rel CJNE Rn,#data rel CJNE @Ri,#data,rel DJNZ Rn,rel DJNZ direct,rel NOP Description Absolute subroutine call Long subroutine call from subroutine from interrupt Absolute jump Long jump Short jump (relative addr.) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immed. to reg. and jump if not equal Compare immed. to ind. and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation Byte 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Special Function Registers
Preliminary Data Sheet
As of Production Version 00
The IA8044/IA8344 contains the following special function registers: ACC B PSW SP DPTR P0 P1 P2 P3 IP IE TMOD TCON TH0 TL0 TH1 TL1 SMD STS NSNR STAD TBS TBL TCB RBS RBL RFL RCB DMA CNT FIFO SIUST Accumulator B register * program Status Word * Stack Pointer Data Pointer (DPH and DPL) Port 0 * Port 1 * Port 2 * Port 3 * Interrupt Priority * Interrupt Enable * Timer/Counter Mode Timer/Counter Control * Timer/Counter 0 high byte Timer/Counter 0 low byte Timer/Counter 1 high byte Timer/Counter 1 low byte Serial Mode SIU Status and Command * SIU Send/Receive Count * SIU Station Address Transmit Buffer Start Address Transmit Buffer Length Transmit Control Byte Receive Buffer Start Address Receive Buffer Length Receive Field Length Receive Control Byte DMA Count FIFO contents (3 bytes) SIU State Counter
* - These registers are bit addressable.
Ports
Ports P0, P1, P2 and P3 are Special Function Registers. The contents of the SFR can be observed on corresponding pins on the chip. Writing a `1' to any of the ports causes the corresponding pin to be at high level (VCC), and writing a `0' causes the corresponding pin to be held at low level (GND). All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P3), an output driver, and an input buffer, so the CPU can output or read data through any
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
of these ports if they are not used for alternate purposes.
Preliminary Data Sheet
As of Production Version 00
Ports P0, P1, P2 and P3 can perform some alternate functions. Ports P0 and P2 are used to access external memory. In this case, port `p0' outputs the multiplexed lower 8 bits of address with `ale' strobe high and then reads/writes 8 bits of data. Port P2 outputs the higher 8 bits of address. Keeping `ea' pin low (tied to GND) activates this alternate function for ports P0 and P2. Port P3 and P1 can perform some alternate functions. The pins of Port P3 are multifunctional. They can perform additional functions as shown below. Pin P3.0 Symbol RxD Function Serial input pin. Setting the appropriate bits in the Special Function Register SCON activates this function. Serial input data at pin P3.0 is strobed to the serial input register and can then be read by the CPU from the Special Function Register SBUF. Serial output pin. Setting the appropriate bits in the Special Function Register SCON and writing data to be transmitted to the Special Function Register SBUF activates this function. Note that SBUF is used to read and transmit data. The function it performs is determined by the CPU operation (read or write). External interrupt 0 is activated on the falling edge by setting the appropriate bits in Special Function Register IE (Interrupt Enable) External interrupt 1 is activated on the falling edge by setting the appropriate bits in the Special Function Register IE (Interrupt Enable) Timer/Counter 0 external input. Setting the appropriate bits in the Special Function Registers TCON and TMOD activates this function. Timer/Counter 1 external input. Setting the appropriate bits in the Special Function Registers TCON and TMOD activates this function. External Data Memory write strobe, active LOW. This function is activated by a CPU write access to External Data Memory (MOV @DPTR, A). External Data Memory read strobe, active LOW. This function is activated by a CPU read access to External Data Memory (MOV A, @DPTR). Request To Send output. Clear To Send input.
P3.1
TxD
P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
INT0 INT1 T0 T1 WR RD
P1.6 P1.7
RTS CTS
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Timers/Counters Timers 0 and 1
Preliminary Data Sheet
As of Production Version 00
The C8051 has two 16-bit timer/counter registers: Timer 0 and Timer 1. Both can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, which means that it counts up after every 12 oscillator periods. In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0 or T1. Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle (12 clock periods). Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Reset
Preliminary Data Sheet
As of Production Version 00
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by generating an internal reset, which is executed during the second cycle in which RST is high. The internal reset sequence writes `0's to all SFRs except the port-latches, the Stack Pointer, SIUST and unused bits of registers.
Reset Values
Register PC ACC B PSW SP DPTR P0 - P3 IP IE TMOD TCON TH0 TL0 TH1 TL1 SMD STS NSNR STAD TBS TBL TCB RBS RBL RFL RCB DMA CNT FIFO1 FIFO2 FIFO3 SIUST Reset value 0000H 00000000B 00000000B 00000000B 00000111B 0000H 11111111B XXX00000B 0XX00000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000001B
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Interrupts
Preliminary Data Sheet
As of Production Version 00
The IA8044/IA8344 provides 5 interrupt sources. There are 2 external interrupts accessible through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are, also, internal interrupts associated with Timer 0 and Timer 1, and an internal interrupt from the SIU.
External Interrupts
The choice between external interrupt level or transition activity is made by setting IT1 and IT0 bits in the Special Function Register TCON. When the interrupt event happens, a corresponding Interrupt Control Bit is set (IT0 or IT1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled. When the interrupt service routine is vectored, the corresponding control bit (IT0 or IT1) is cleared provided that the edge triggered mode was selected. If level mode is active, the external requesting source controls flags IT0 or IT1 by the logic level on pins INT0 or INT1 (0 or 1).
Timer0 and Timer 1 Interrupts
Timer 0 and 1 interrupts are generated by TF0 and TF1 flags, which are set by the rollover of Timer 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is cleared by the hardware, if the CPU accessed the corresponding interrupt service vector. This can be done only if this interrupt is enabled in the IE register.
Serial Interface Unit Interrupt
The SIU generates an interrupt when a frame is received or transmitted. No interrupts are generated for a received frame with errors.
Interrupt Priority Level Structure
There are two priority levels in the IA8044/IA8344, and any interrupt can be individually programmed to a high or low priority level. Modifying the appropriate bits in the Special Function Register IP can accomplish this. A low priority interrupt service routine will be interrupted by a high priority interrupt. However, the high priority interrupt can not be interrupted. If two interrupts of the same priority level occur, an internal polling sequence determines which of them will be processed first. This polling sequence is a second priority structure defined as follows: IE0 1 - highest TF0 2 IE1 3 TF1 4 SIU - lowest
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Interrupt Handling
Preliminary Data Sheet
As of Production Version 00
The interrupt flags are sampled during each machine cycle. The samples are polled during the next machine cycle. If an interrupt flag is captured, the interrupt system will generate an LCALL instruction to the appropriate service routine, provided that this is not disabled by the following conditions: 1. An interrupt of the same or higher priority is processed 2. The current machine cycle is not the last cycle of the instruction (the instruction can not be interrupted). 3. The instruction in progress is RETI or any write to IE or IP registers. Note that if an interrupt is disabled and the interrupt flag is cleared before the blocking condition is removed, no interrupt will be generated, since the polling cycle will not sample any active interrupt condition. In other words, the interrupt condition is not remembered. Every polling cycle is new.
SIU - Serial Interface Unit
The SIU is a serial interface customized to support SDLC/HDLC protocol. As such it supports Zero Bit insertion/deletion, Flags automatic access recognition and a 16 bit CRC. The SIU has two modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC protocol implemented in hardware. This frees the CPU from having to respond to every frame but limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore more options are available. The SIU is controlled by and communicates to the CPU by using several special function registers (SFRs). Data transmitted to or received by the SIU is stored in the 192 byte internal RAM in blocks referred to as the transmit and receive buffers. The SIU can support operation in one of three serial data link configurations: 1) half-duplex, point-to-point, 2) half-duplex, multipoint, 3) loop.
SIU Special Function Registers
The CPU controls the SIU and receives status from the SIU via eleven special function registers. The Serial Interface Unit Control Registers are detailed below:
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Serial Mode Register (SMD):
Preliminary Data Sheet
As of Production Version 00
The serial mode register sets the operational mode of the SIU. The CPU can read and write SMD. The SIU can read SMD. To prevent conflicts between CPU and SIU accesses to SMD the CPU should write SMD only when RTS and RBE bits in the STS register are both zero. SMD is normally only accessed during initialization. This register is byte addressable. SMD (C9H) Bit: 7 6 5 4 3 2 1 0 SCM2 SCM1 SCM0 NRZ LOO PFS NB NFCS I P SMD.0 SMD.1 SMD.2 NFCS NB PFS When set selects No FCS field contained in the SDLC frame. Non-buffered mode. No control field contained in SDLC frame. Pre-frame sync mode. When set causes two bytes to be transmitted before the first flag of the frame for DPLL synchronization. If NRZI is set 00H is transmitted otherwise 55H. This ensures that 16 transitions are sent. When set selects loop configuration. When set selects NRZI encoding otherwise NRZ. Select clock mode - bit 0. Select clock mode - bit 1. Select clock mode - bit 2.
SMD.3 SMD.4 SMD.5 SMD.6 SMD.7
LOOP NRZI SCM0 SCM1 SCM2
SMD Select Clock Mode Bits
SCM 210 000 001 010 011 100 101 110 111 Clock Mode Data Rate (Bits/sec)* 0 - 2.4M**
Externally clocked Undefined Self clocked, timer overflow 244 - 62.5K Undefined Self clocked, external 16X 0 - 375K Self clocked, external 32X 0 - 187.5K Self clocked, internal fixed 375K Self clocked, internal fixed 187.5K * based on a12 MHz crystal frequency ** 0 - 1M bps in loop configuration
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Status/Command Register (STS):
Preliminary Data Sheet
As of Production Version 00
The Status/Command register provides SIU control from and status to the CPU. The SIU can read the STS and can write certain bits in the STS. The CPU can read and write the STS. Accessing the STS by the CPU via 2 cycle instructions (JBC bit,rel and MOV bit,C) should not be used. STS is bit addressable. STS (C8H) Bit: 7 TBF STS.0 STS.1 STS.2 STS.3 STS.4 STS.5 STS.6 STS.7 6 RBE RBP AM OPB BOV SI RTS RBE TBF 5 RTS 4 SI 3 BOV 2 OPB 1 AM 0 RBP
Receive buffer protect. When set prevents writing of data into the receive buffer. Causes RNR response instead of RR in AUTO mode. Auto mode. If NB is cleared AM selects the AUTO mode when set. If NB is set AM selects the addressed mode when set. The SIU can clear AM. Optional poll bit. When set the SIU will AUTO respond to an optional poll (UP with P=0). The SIU can set or clear the OPB. Receive buffer overrun. The SIU can set or clear BOV. SIU interrupt. This bit is set by the SIU and should be cleared by the CPU before returning from the interrupt routine. Request to send. This bit is set when the SIU is ready to transmit or is transmitting. May be written by the SIU in AUTO mode. Receive buffer empty. RBE is set by the CPU when it is ready to receive a frame or has just read the buffer. It is cleared by the SIU when a frame has been received. Transmit buffer full. TBF is set by the CPU to indicate that the transmit buffer is ready and cleared by the SIU.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Send/Receive count register (NSNR):
Preliminary Data Sheet
As of Production Version 00
The NSNR contains both the transmit and receive sequence numbers in addition to the tally error indications. The CPU can read and write the STS. Accessing the STS by the CPU via 2 cycle instructions (JBC bit,rel and MOV bit,C) should not be used. The SIU can read and write the NSNR. NSNR is bit addressable. NSNR (D8H) Bit: 7 NS2 NSNR.0 NSNR.1 NSNR.2 NSNR.3 NSNR.4 NSNR.5 NSNR.6 NSNR.7 6 NS1 SER NR0 NR1 NR2 SES NS0 NS1 NS2 5 NS0 4 SES 3 NR2 2 NR1 1 0 NR0 SER
Sequence error receive. NS (P) ? NR (S). Receive sequence counter, Bit 0. Receive sequence counter, Bit 1. Receive sequence counter, Bit 2. Sequence error send. NR (P) ? NS (S) and NR (P) ? NS (S) + 1. Send sequence counter, Bit 0. Send sequence counter, Bit 1. Send sequence counter, Bit 2.
Data Clocking Options
The SIU may be clocked in one of two ways, with an external clock or in a self-clocked mode. In the external clocked mode a serial clock must be provided on SCLK. This clock must be synchronized to the serial data. Incoming data is sampled at the rising edge of SCLK. Outgoing data is shifted out at the falling edge of SCLK. In the self-clocked mode the SIU uses a reference clock and the serial data to reproduce the serial data clock. The reference clock can be an external source applied to SCLK, the IA8044/IA8344's internal clock or the timer 1 overflow. The reference clock must be 16x or 32x the data rate. A DPLL uses the reference clock and the serial data to adjust the sample time to the center of the serial bit. It does this by adjusting from a serial data transition in increments of 1/16 of a bit time. The maximum data rate in the externally clocked mode is 2.4Mbps in half-duplex configuration and 1.0Mbps in a loop configuration. The maximum data rate in the self-clocked mode with an external clock is 375Kbps. The maximum data rate in the self-clocked mode with an internal clock will depend on the frequency of the IA8044/IA8344's input clock. An IA8044/IA8344 using a 12MHz input clock can operate at a maximum data rate of 375Kbps.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Operational Modes
Preliminary Data Sheet
As of Production Version 00
The SIU operates in one of two modes, AUTO or FLEXIBLE. The mode selected determines how much intervention is required by the CPU when receiving frames. In both modes short frames, aborted frames, and frames with CRC errors will be ignored. AUTO mode allows the SIU to recognize and respond to specific SDLC frames without the CPUs intervention. This provides for a faster turnaround time but restricts the operation of the SIU. When in AUTO mode the SIU can only act as a normal response secondary station and responses will adhere to IBM's SDLC definitions. When receiving in the AUTO mode the SIU receives the frame and examines the control byte. It will then take the appropriate action for that frame. If the frame is an information frame the SIU will load the receive buffer, interrupt the CPU and make the required response to the primary station. The SIU in AUTO mode can also respond to the following commands from the primary station. RR (Receive ready), RNR (Receive Not Ready), REJ (Reject), UP (Unnumbered Poll) also called NSP (Non-Sequenced Poll) or ORP (Optional Response Poll). In AUTO mode when the transmit buffer is full the SIU can transmit an information frame when polled for information. After transmission the SIU waits for acknowledgement from the receiving station. If the response is positive the SIU interrupts the CPU. If the response is negative the SIU retransmits the frame. The SIU can send the following responses to the primary station. RR (Receive Ready), RNR (Receive Not Ready). The FLEXIBLE mode requires the CPU to control the SIU for both transmitting and receiving. This slows response time but allows full SDLC and HDLC compatibility as well as variations. In FLEXIBLE mode the SIU can act as a primary station. The SIU will interrupt the CPU after completion of a transmission without waiting for a positive acknowledgement from the receiving station.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Frame Format Options
Preliminary Data Sheet
As of Production Version 00
The various frame formats available with the IA8044/IA8344 are the standard SDLC format, the no control field format, the no control field and no address field format and the no FCS field format. The standard SDLC format consists of an opening flag, an 8-bit address field, an 8-bit control field, and n-byte information field, a 16-bit frame check sequence field and a closing flag. The FCS is generated by the CCIT-CRC polynomial (X16 +X12 + X5 + 1). The address and control fields may not be extended. The address is contained in STAD and the control filed is contained in either RCB or TCB. This format is supported by both AUTO and FLEXIBLE modes. The no control field format is only supported by the FLEXIBLE mode. In this format TCB and RCB are not used and the information field starts immediately after the address field. The no control field and no address field format is only supported by the FLEXIBLE mode. In this format STAD, TCB and RCB are not used and the information field starts immediately after the opening flag. This option can only be used with the no control field option. The no FCS field format prevents an FCS from being generated during transmission or being checked during reception. This option may be used in conjunction with the other frame format options. This option will work with both FLEXIBLE and AUTO modes. In AUTO mode it could cause protocol violations.
HDLC Restrictions
The IA8044/IA8344 supports a subset of the HDLC protocol. The differences include the restriction by the IA8044/IA8344 of the serial data to be in 8-bit increments. In contrast HDLC allows for any number of bits in the information field. HDLC provides an unlimited address field and an extended frame number sequencing. HDLC does not support loop configuration.
SIU Details
The SIU is composed of two functional blocks with each having several sub blocks. The two blocks are called the bit processor (BIP) and the byte processor (BYP).
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Bit and Byte Processors
Preliminary Data Sheet
As of Production Version 00
BIP
The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero insertion/deletion, shutoff logic and FCS generation/checking. The NRZI logic compares the current bit to the previous bit to determine if the bit should be inverted. The serial shifter converts the outgoing byte data to bit data and incoming bit data to byte data. The zero insert/delete circuitry inserts and deletes zeros and also detects flags, go-aheads (GA) and aborts. The pattern 1111110 is detected as an early go-ahead that can be turned into a flag in loop configurations. The shutoff detector is a three bit counter that is used to detect a sequence of eight zeros, which is the shutoff command in loop mode transmissions. It is cleared whenever a one is detected. The FCS logic performs the generation and checking of the FCS value according to the polynomial described above. The FCS register is set to all 1's prior to each calculation. If a CRC error is generated on a receive frame the SIU will not interrupt the CPU and the error will be cleared upon receiving an opening flag.
BYP
The BYP contains registers and controllers used to perform the manipulations required for SDLC communications. The BYP registers may be accessed by the CPU (see SFR section above). The BYP contains the SIU state machine which controls transmission and reception of frames.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Diagnostics
Preliminary Data Sheet
As of Production Version 00
A diagnostic mode is included with the IA8044/IA8344 to allow testing of the SIU. Diagnostics use port pins P3.0 and P3.1. Writing a 0 to P3.1 enables the diagnostic mode. When P3.1 is cleared writing data to P3.0 has the effect of writing a serial data stream to the SIU. P3.0 is the serial data and any write to port 3 will clock SCLK. The transmit data may be monitored on P3.1 with any write to port 3 again clocking SCLK. In the test mode P3.0 and P3.1 pins are placed in the high impedance state.
Diagnostic Signal Routing
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
AC/DC Parameters Absolute Maximum Ratings:
Ambient temperature under bias....................................-40C to +85C Storage temperature..........................................................- 40C to 150C Power Supply (VDD)......................................................-0.3 to +6VDC Voltage on any pin to VSS...............................................-0.3 to (VDD +0.3) Power dissipation......................................................................See Note 1
DC Characteristics
Symbol VIL VIH VOL VOH RPU RPD IIL IIL1 IIH IIH1 IOZ ICC CIO Parameter Input Low Voltage Input High Voltage Output Low Voltage (IOL= 4mA) Output High Voltage (IOH= 4mA) Pull-Up Resistance (Ports 1,2,3) Pull-Down Resistance (RST) Input Low Current (Ports 1, 2, 3) Input Low Current (all other inputs) Input High Current (RST) Input High Current (all other inputs) Tri-state Leakage Current (Port 0,1,2,3) Power Supply Current: Pin Capacitance Min 2.0 3.5 -100 -1 -1 -1 -10 Typ 50 50 Unit V V V V A mA A A A See Note 1 mA pF Max 0.8 0.4 1 1 100 1 10
-
4
Notes: 1. Power dissipation characterization is in progress. Values will be provided upon completion of this process.
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
A.C. Characteristics1
External Program Memory Characteristics
Symbol TLHLL TAVLL 2 TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX 3 TPXIZ 3 TPXAV TAVIV TAZPL Parameter ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr. In. ALE Low to PSENn Low PSENn Pulse Width PSENn Low to Valid Instr. In Input Instr. Hold After PSENn Input Instr. Float After PSENn PSENn to Address Valid Address to Valid Instr. In Address Float to PSENn 12 MHz Osc Min Max Variable Clock 1/TCLCL = 3.5 MHz TO 12 MHz Min Max Unit ns ns ns ns ns
ns ns ns ns
Notes: 1. Actual values will provided for the External Program Memory Characteristics, External Data Memory Characteristics, and Serial Interface Characteristics tables (pp. 26 - 27) upon completion of device testing. Values from the original device data sheet may be used to characterize parameters in the interim. 2.TLLAX for access to program memory is different from TLLAX for data memory. 3. Interfacing RUPI-44 devices with float times up to 75ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER External Data Memory Characteristics
Symbol TRLRH TWLWH TLLAX TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RDn Pulse Width WRn Pulse Width Address Hold After ALE RDn Low to Valid Data In. Data Hold After RDn Data Float After RDn ALE Low to Valid Data In Address to Valid Data In. ALE Low to RDn or WRn Low Address to RDn or WRn Low Data Valid to WRn Transistion Data Setup Before WRn High Data Held After WRn RDn Low to Address Float RDn or WRn High to ALE High
Preliminary Data Sheet
As of Production Version 00
12 MHz Osc Min Max
Variable Clock 1/TCLCL = 3.5 MHz TO 12 MHz
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max
Serial Interface Characteristics
Symbol TDCY TDCL TDCH tTD tDSS tDHS Parameter Data Clock Data Clock Low Data Clock High Transmit Data Delay Data Setup Time Data Hold Time Min Max Unit ns ns ns ns ns ns
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER Waveforms Memory Access
Program Memory Read Cycle
Preliminary Data Sheet
As of Production Version 00
TCY TLHLL TLLIV TLLPL ALE
TPLPH PSENn TPXAV TAVLL PORT_0 INSTR. IN A7-A0 TAZPL TLLAX TPLIV TPXIZ INSTR. IN TPXIX A7-A0 INSTR. IN
TAVIV PORT_2
ADDRESS OR SFR-P2
ADDRESS A15-A8
ADDRESS A15-A8
Data Memory Read Cycle
TLLDV ALE TWHLH
PSENn
TLLWL RDn
TRLRH
TAVDV TAVWL TLLAX PORT_0 A7-A0 TRLDV DATA IN TRLAZ TRHDX TRHDZ
PORT_2
ADDRESS A15-A8 OR SFR-P2
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Memory Write Cycle
TWHLH ALE
Preliminary Data Sheet
As of Production Version 00
PSENn TLLWL WRn TWLWH
TQVWH TLLAX TAVWL TQVWX PORT_0 A7-A0 DATA OUT TWHQX
PORT_2
ADDRESS A15-A8 or SFR-P2
Serial I/O Waveforms
Synchronous Data Transmission
TDCY TDCL SCLK TDCH
TTD DATA
Synchronous Data Reception
TDCY TDCL SCLK TDCH
TDSS DATA
TDHS
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Packaging Information
PLCC Package
D D1
0.045*45o
PIN 1 IDENTIFIER & ZONE
D3 TOP VIEW
E1
E
E3
0.026-0.032
BOTTOM VIEW
Package Dimensions for 44 Lead PLCC
SEATING PLANE A
Symbol A A1 D1 D2 D3 E1 E2 E3 e D E
e .02 MIN.
0.013-0.021
.004
R 0.035
D2 / E2
SIDE VIEW
Typical (in Inches) 0.180 0.110 0.653 0.610 0.500 0.653 0.610 0.500 0.050 0.690 0.690
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A1
IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
PDIP Package
TOP
E1
E
LEAD 1 IDENTIFIER
C eB
1 LEAD COUNT DIRECTION
SIDE VIEW (WIDTH)
D
A
Package Dimensions for 40 Lead PDIP (600 mil.) Symbol Typical (in Inches)
A1
L B B1 e
A A1 B B1 C D E E1 e eB L
0.155 0.010 0.018 0.050 0.010 2.055 0.600 0.545 0.100 0.650 0.130
SIDE VIEW (LENGTH)
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IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
* Ordering Information
Part Number IA8044-PDW40I-00 IA8044-PLC44I-00 IA8344-PDW40I-00 IA8344-PLC44I-00 Temperature Grade Industrial Industrial Industrial Industrial
* Cross Reference to Original Part Numbers
innovASIC Part Number IA8044-PLC44I
q q
Intel(R) Part Number N8044AH N8044AH-R0117 P8044 P8044AH P8044AH-R0117 TP8044AH TP8044AH-R0117
IA8044-PDW40I
q q q q q
IA8344-PLC44I
q q
N8344AH TN8344AH P8344 P8344AH TP8344AH
IA8344-PDW40I
q q q
* Errata
There is no errata for this device.
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